Many integrated circuits communicate multiple bits of digital data in parallel at various times in their operation by way of an internal data bus, consisting of a set of parallel conductors to which multiple circuit functions are connected. In particular, memory circuits often include a data bus to facilitate access from memory cells at various locations within the chip. For example, an internal data bus is particularly useful in memories organized into sub-arrays, or blocks of memory cells, where access of a selected memory cell does not require enabling of the entire memory device. The resulting power savings makes such partitioned memory arrays especially useful in low power memories for portable computers.
Modern memory circuits are required to operate at high speeds while being fabricated with the highest density technology. In such memories, the series resistance and parasitic capacitance of relatively long conductors, such as data bus lies, can become a significant factor in the operating performance of the memory, as such parasitic capacitance affects the time required for the conductor to switch from one digital state to the other. Furthermore, as memory circuits become increasingly dense, the cross-sectional area allowable for the data bus conductors decreases, in turn increasing the resistance of the data bus conductors and increasing the time constant of its switching, particularly if the data bus conductor must fully switch between ground and the power supply voltage (i.e., from "rail to rail").
Of course, the increased R-C load of the data bus conductors can be overcome by increasing the size of the transistors driving the bus. Increases in the size of transistors of course runs counter to the desire to increase the density of memory integrated circuits. Furthermore, the driver transistors must fit within the "pitch" allowed for their associated sense amplifier, as any excess size will directly affect the chip size, and thus the manufacturing cost of the integrated circuit; indeed, the capacitance added to the data bus by the drivers themselves, where multiple drivers are driving the same bus, can outweigh the benefit of the larger drive capacity. Furthermore, in some cases the R-C load of the data bus may be too great for any reasonably sized driver to meet the desired switching time from rail to rail.
It is therefore an object of this invention to provide a technique for precharging data bus conductors, between cycles, prior to the application of a data signal thereto.
It is a further object of this invention to provide such a technique which is closely matched to the construction of the data bus conductors.
It is a further object of this invention to provide such a technique incorporating a dummy data bus conductor, and in which floating conditions on the dummy data bus conductor are avoided.
It is a further object of this invention to provide such a technique which precharges the data bus conductor near the trip point of the output stage, without risking oscillations.
Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.